Hi all

After the success of running "Hello world" with minsoc and testing UART with Spartan-3E. Now is turn of Ethernet, when we can now run "hello world" and testing the communication with Ethernet. So the principal steps for this are :

1 ) go and download the latest project of minosoc
http://opencores.com/project,minsoc

2) open the doc Howto and read the steps for simulation and implementation.

So, just 2 steps and you have a SOC running in your board Spartan-3E500 starter Kits.

System Features

-or1200 OpenRISC implementation

-Resizable onchip memory

-System frequency selection

-JTAG debug featuring a multitude of cables

-UART and Ethernet modules

-FPGA independent and dependent code (spartan-3E500) for memory, clock adaptation (DCMs) and JTAG Tap

-System configuration in a single definition file

-Example firmwares using UART and Ethernet

-Testbench included, for the simulation of exactly your configured system.

Many thanks to Raul and good luck.

Hi Bakiri,

I am trying to implement the minsoc with ethernet on my Spartan 3E500 starter kit. I followed the "howto" doc in minsoc project folder. I met this error of "Too many comps of type RAMB16" during the "Map" step in implementation. The Design summary indicates the usage of RAMB16s is 23 while spartan 3E500 only have 20 of them.
Do you have any suggestion of what I should do to meet this limitation?
Thank you very much!

Regards.

Zhengyu

Hi yangz2

first confirm you have do this steps : confirm the first 1)

1) minsoc/rtl/verilog/minsoc_defines.v => change MEMORY_ADR_WIDTH from 13 to 12

2) minsoc/rtl/verilog/or1200/rtl/verilog/or1200_defines.v =>
� uncomment `define OR1200_XILINX_RAMB16
� comment `define OR1200_MULT_IMPLEMENTED
� comment `define OR1200_MAC_IMPLEMENTED
� uncomment `define OR1200_RFRAM_DUALPORT
� comment `define OR1200_RFRAM_GENERIC

3)minsoc/rtl/verilog/ethmac/rtl/verilog/eth_defines.v =>
� uncomment `define ETH_FIFO_XILINX
� uncomment `define ETH_XILINX_RAMB4

4) adv_debug_system => disable jsp in step 5
configure minsoc/rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v
=> comment out line 67, �`define DBG_JSP_SUPPORTED�

thats all, it's work fine

Hi Bakiri:
I am planning to put the minsoc on my spartan 3E-1600 development kit, is there any changes need for it? Or is your spartan-3E 500 or 1600?
Thanks.
B.R
Colin Chen

Hi guys:
I guess your boards are 3E500. Mine is 3E 1600, could you please tell me if i need to do some changes for running the code on the 3E1600 board.
Thanks.
Colin Chen

Hi colin

because you have spartan-3E1600 that is big than 3E500, you can just keep the default configuration like Spartan-3A1800 of Raul (memory and clock)without disabling anything,

the clock are the same for all bord of Spartan-3E and spartan-3A.

there is also a wiki page for minsoc project if you want know more and fix a future problem as adv_debug_system http://minsoc.wikaba.com/

Hi Bakiri:
Thanks for the help. I have programmed the bits into the fpga and run the uart code successfully through the gdb. The feeling is great. Now the next step i am thinking is how to support the external dram on the board, my final goal is to run the linux on the fpga with ethernet/uart.
B.R
Colin Chen

Hello ,

I am trying to implement Minsoc on Spartan 3E 500. I have followed all the steps. I am now having problems with using the Jtag[DLC9] cable for downloading the design. I am using Impact to dowmload the bit file on to the board. After the bit file is downloaded I am unable to use the cable with the adv_jtag_debugger. Could anyone of you please let me know what are the possible options do I have. I want to use the debugger too. I did explore some options which include downloading the file to the SPI memory do that the device can self configure on start up , but I cannot use the debugger with that.

Did anyone of you have sucess using the adv debugger?

Thanks
Prathyusha

Hi,

If someone has success with building minsoc with ethernet mac for spartan-3e 1600 and is willing to share his/her experience, the info will be highly appreciated.



Following the advices given at this thread as well as at http://www.minsoc.com/ and finally reaching http://www.minsoc.com/1_0:synthesis
after `make all` I get:

Design Information
------------------
Command Line : map -bp -timing -cm speed -equivalent_register_removal on
-logic_opt on -ol high -power off -register_duplication on -retiming on -w -xe n
minsoc.ngd
Target Device : xc3s1600e
Target Package : fg320
Target Speed : -4
Mapper Version : spartan3e -- $Revision: 1.51 $
Mapped Date : Wed Mar 21 19:32:32 2012

Interim Summary
---------------
Logic Utilization:
Number of Slice Flip Flops: 3,869 out of 29,504 13%
Number of SLICEMs: 18,527 out of 7,376 251% (OVERMAPPED)
(SLICEMs can only be placed in SLICEM sites.)
Number of 4 input LUTs: 55,014 out of 29,504 186% (OVERMAPPED)
Logic Distribution:
Number of Slices containing only related logic: 32,327 out of 32,327 100%
Number of Slices containing unrelated logic: 0 out of 32,327 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 55,390 out of 29,504 187% (OVERMAPPED)
Number used as logic: 22,083
Number used as a route-thru: 376
Number used for Dual Port RAMs: 32,928
(Two LUTs used per Dual Port RAM)
Number used as Shift registers: 3

The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.

Number of bonded IOBs: 30 out of 250 12%
Number of RAMB16s: 7 out of 36 19%
Number of BUFGMUXs: 5 out of 24 20%

It seems that I am doing something ( probably many things ) wrong in order to succeed overmapping such a big (comparatively big) device.
Any idea, what could be touched in order to be able to reduce the size of the design?

Regards & Thanks,

Stoev

The "overmapping" issue of previous post was resolved.
After reading again "Minimal OpenRISC System on Chip How to", especially

7. Examples
...
3. Spartan 3E Starter Kit with Ethernet (not tested)

I realized that was trying to generate bit stream against SPARTAN3A and not SPARTAN3E ( the board I have )
After commenting and uncommenting according to the examples ( I had to comment`define UART too ) and running
make clean all
2 times (the first time it spit "PAR done! make: *** [minsoc_par.ncd] Error 31" at the end)
minsoc.bit was generated.

Regards,

Stoev

Hi, I followed these instructions and I kept getting an error on the pins of the wishbone interface of adbg not existing. (wb_jsp_adr_i, etc). It turns out that in the minsoc_top.v (line 474), these pins are connected to signals, even if "JSP" is not defined. It seems that when I commented out `define DBG_JSP_SUPPORTED (line 67 of dbg_defines.v), those pins were taken out of that module's top level.

I fixed that in minsoc_top.v, by just not mentioning those I/Os when JSP is not defined, and now is working. But I would like to double check that there was actually something to fix in the source code, or if I am just messing up with the code unnecesarily.
Thanks for your help,